(1) Field of the Invention
This invention relates to the in-line monitoring of photo processing steps in integrated circuit wafer fabrication and, more particularly, to the use of a de-focus pattern formed on the wafer between circuit chips to monitor photo process steps.
(2) Description of the Related Art
U.S. Pat. No. 5,556,726 to Yuan describes a method of determining quantitatively the exposure levels for photoresists using a specially designed grating on a mask.
U.S. Pat. No. 5,496,669 to Pforr et al. describes a latent image detection device comprising an alignment device intended for aligning the mask pattern with respect to the substrate. The invention also describes a focus test pattern on the product wafer that allows in-line measurement of substrate height and focus.
U.S. Pat. No. 5,447,810 to Chen et al. describes a method of using off-axis illumination mask to increase depth of focus and minimize critical dimension differences between some features.
U.S. Pat. No. 5,439,767 to Yamashita et al. describes a method of inspecting the transmittance error of a phase shift mask.
U.S. Pat. No. 5,483,056 to Imai describes a method of detecting an amount of de-focus for a projection exposure system using a focus detection system. A substrate is then loaded into the system and moved to a predetermined height by a Z-stage movable in the axial direction, using the amount of de-focus information, thereby exposing the shot area of the mask to the mask pattern.
TSMC-96-161, Serial No. , Entitled "Opposite Focus Control to Avoid Keyholes Inside a Passivation Layer," assigned to the same signee, describes the use of intentional de-focus to avoid keyholes or areas having a trapezoidal cross section in a dielectric layer.
The present invention describes a de-focus test pattern and a method for in-line monitoring of photo processing steps in the fabrication of integrated circuit wafers. The de-focus pattern is located on the product wafer and is formed as the product wafer is formed. The de-focus pattern has test patterns at a number of heights above the surface of the integrated circuit wafer. The amount of de-focus of a particular process can be readily monitored in-line. The de-focus pattern is located at the edges of a field so the relative tilt between the wafer and a photo mask can readily be monitored.